The present invention relates to a single chip microcomputer and, more particularly, to such a microcomputer having an analog-to-digital (A/D) converter of a capacitor/resistor (C/R) type as one of peripheral units.
Aa well known in the art, a single chip microcomputer includes, on a single semiconductor chip, a program memory storing a string of instructions for a program, a data memory storing operand data, a central processing unit (CPU) performing a data processing operation on the operand data stored in the data memory in accordance with the instruction read out from the program memory, and a plurality of peripheral units such as an A/D converter, a digital-to-analog converter, a serial data communication unit and a timer/counter. Although a various types of A/D converters are known in the art, an A/D converter of a C/R type has been put into practical use as a peripheral unit of the microcomputer. The A/D converter of this type includes a capacitor circuit for generating more (or less) significant bits of digital data corresponding to an analog input signal and a resistor circuit for generating less (or more) significant bits of the digital data.
Referring to FIG. 1, a microcomputer according to prior art includes a CPU 101 and an A/D converter 100 of the C/R type which are interconnected through an internal bus 107. The converter 100 includes a sequence controller 102, a capacitor circuit 103, a resistor circuit 104 and a comparator 106. The sequence controller 102 receives control data from and supplies converter digital data to the CPU 101 via the bus 107. The capacitor circuit 103 is supplied with an analog input signal Aid via a signal line 110 and coupled to the controller 102 via a control signal bus 108 to control electrical charges to be stored in capacitors (see FIG. 2). The output voltage from the capacitor circuit 103 appears on a line 114. The resistor circuit 104 is coupled to the controller 102 via a control signal bus 109 to generate and supply a selected voltage to the capacitor circuit 103 through a line 116. The comparator 106 compares the output voltage on the line 114 with a reference voltage VA on a line 113.
Referring to FIG. 2, the capacitor circuit 103 includes three capacitors 605-607 and four switch circuits 601-604 which are connected as shown. The capacitance ratio of the capacitors 605, 606 and 607 is 1:1:2. The switch circuit 601 connects the lines 113 and 114 to each other when the control data on a control signal line 608 of the control bus 108 assumes the high level and disconnects them from each other when the control data assumes the low level. The high level of the control data on the line 608 further causes the switch circuits 602, 603 and 604 to connect the analog input line 110 to the respective one ends of the capacitors 605, 606 and 607. When the control data 608 is at the low level, on the other hand, the line 116 is connected to the one end of the capacitor 605 through the switch 602. As to the switch circuits 603 and 604, the switch circuit 603 connects the one end of the capacitor 606 to the analog ground voltage AVss when both of the control data 608 and 610 of the control data bus 108 assume the low level and to another reference voltage Vref when the control data 608 and 610 assume the low level and the high level, respectively. The switch circuit 604 connects the one end of the capacitor 604 to the analog voltage AVss when both of the control data 608 and 609 take the low level and to the reference voltage Vref when the control data 608 and 609 take the low level and the high level, respectively.
Turning to FIG. 3, the resistor circuit 104 includes a plurality of resistors 707-711 connected in series between the reference voltage Vref and the analog ground AVss and a plurality of transfer gates 701-706. Each of the transfer gates 701-706 is connected between the different one of the connection nodes of the resistors 707-711 and the voltage output line 116. The conductive and nonconductive states of transfer gates 701-706 are controlled by the corresponding control data 712-717 of the control bus 109.
In operation, the CPU 101 supplies the conversion control data to the sequence controller 102 via the internal bus 107 to command the conversion operation. In response thereto, the controller 102 initiates first a sampling operation in which the control data 608 is changed to the high level to cause the switch circuit 601 to connect the lines 113 and 114 to each other. The switch circuits 602-604 connects the analog input line 110 to the respective one ends of the capacitors 605-607. Consequently, the capacitors 605-607 receive the analog input signal Aid at the respective one ends thereof and the reference voltage VA at the respective other end thereof, and store the voltage difference therebetween.
Subsequently, an conversion operation is initiated to change the control data 608 to the low level. The switch circuit 601 is thereby tuned OFF and the switch circuit 602 connects the lines 116 and 611 to each other. In a first step, the control data 609 and 610 are brought into the high level and low level, respectively. The switch circuit 604 supplies the reference voltage Vref to the one end of the capacitor 607. The electrical charges stored in the capacitors 605-607 are thereby increased to push up the voltage on the line 114. The comparator 106 compares the voltage on the line 114 thus push up with the voltage VA and supplies the comparison result to the controller 102. The output of the comparator 106 indicates the most significant bit data of the converted digital data. The logic level of the control data 609 is thereby determined.
In a next step, The control data 610 is changed to the high level to cause the switch circuit 603 to supply the reference voltage Vref to the one end of the capacitor 606. The electrical charges stored in the capacitors 605-607 are thereby increased to rise the voltage of the line 114. The comparator 106 outputs the comparison data which represents the next most significant bit data of the converted digital data. Thus, the capacitor circuit 103 generates the most significant two bit data of the converted digital data.
The remaining bit data of the converted digital data are derived by the resistor circuit 104. More specifically, one of the transfer gates 701-706 is turned ON such that the voltage on the line 116 takes the intermediate level of the reference voltage Vref. The electrical charges stored in the capacitors 605-607 are thereby increased in accordance with the voltage on the line 116 and the capacitance of the capacitor 605. The output of the comparator 106 thus indicates the third most significant bit data of the converted digital data. In a similar manner, one of the transfer gates 701-706 to be turned ON is controlled to obtain the remaining bit data of the converted digital data. The digital data thus converted is supplied to the CPU 101 from the sequence controller 101 through the internal bus 107.
As apparent from the above description, the conversion accuracy is dependent on the actual values of each of the capacitors 605-607 and resistors 707-711. Accordingly, it is desirable to check whether each of the capacitors 605-607 and resistors 707-711 is within the tolerant range. It is further required to check the capacitor circuit and the resistor circuit independently of each other.